Pre-processing Block Hardware Architecture in Image Processing using Reconfigurable Platform

Chiranjeevi G N

Abstract


Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic requiments viz duplicating, zero padding. For K x K kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software based processing for K x K spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block



DOI: https://doi.org/10.11591/csit.v3i1.p%25p

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Computer Science and Information Technologies
ISSN: 2722-323X, e-ISSN: 2722-3221

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